Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost. An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
A well-studied occurrence in circuitry is called “Single Event Upset.” Single Event Upset or SEU is a change in state of a circuit, conventionally a bit storing circuit such as a dynamic random access memory (DRAM) cell, latch, static random access memory (SRAM) cell and the like, caused by an external energy source, such as alpha particles, cosmic rays, energetic neutrons and the like. The seriousness of SEU is increasing as transistor channel length, oxide thickness, and width continue to decrease. Since the geometries have moved to less than 0.25 microns, the problem has been significant enough that efforts are being made to overcome or decrease the seriousness of SEU events.
In a conventional DRAM or SRAM, an SEU may be addressed with error correction. In fact, error-correcting memory is widely commercially available. However, this is not an efficient option for memory used to configure an FPGA, because configuration memory cells are used to define how the CLBs, IOBs, and interconnect structure are configured. Because an individual memory cell is used for control, conventionally without decoding, if a memory cell changes state owing to an SEU, then a logic function under control of such a memory cell may change.
An approach to handling an SEU condition in an FPGA is triple modular redundancy (TMR), namely, use of three sets of memory cells and configurable logic in place of one, where outcome of at least two of the three sets controls FPGA operation. However, this adds considerable cost.
Others have attempted to increase resiliency to an SEU for a memory cell. Referring to FIG. 1, there is shown a schematic diagram of an SEU hardened memory cell 10 of the prior art. Memory cell 10 is a latch having cross-coupled inverters 12 and 14. Resistors 13 and 15 are coupled to respective outputs of inverters 12 and 14. In order to provide SEU resiliency, resistors 13 and 15 each have a resistance of approximately one mega-ohm. Input voltage, Vin 11, is inverted or complemented by inverter 12 to provide output voltage, Vout 12, which voltage drop is SEU hardened owing to voltage drop across resistor 13, and Vout 12 is inverted by inverter 14 to provide Vin, which voltage drop is SEU hardened owing to voltage drop across resistor 15. Unfortunately, formation of a resistor having a resistance sufficient to harden a latch against an SEU consumes a relatively large amount of area, slows performance, and creates complexity for integration with complementary-metal-oxide semiconductor (CMOS) process. Others have used capacitive loading at an input of an inverter 12 or 14; however, capacitive loading also slows performance of latch 10.
Accordingly, it would be desirable and useful to provide an SEU-resistive memory circuit suitable for integration with a CMOS process. Moreover, it would be desirable and useful to provide an SEU-resistive memory circuit that does not consume as much semiconductor wafer area as other SEU-resistive memory circuits and allows for high speed writing, and high SEU resistance when reading.